According to "Moore's Law" as it is popularly known, the scale of integrated circuit (IC) density has historically doubled once about every 18 to 24 months. IC manufacturers recognize a need to continue increasing the scale of integration at this pace. Manufacturers have not been able to achieve the necessary increase in density merely by using sharper photolithography techniques to linearly shrink the size of features on an IC. Other changes have had to be made, as only some features can be scaled linearly from one IC generation to the next, while other features can be scaled only by a fraction of the reduction in lithographic scale.
Features formed within the first few levels of the semiconductor surface of a wafer are conveniently measured in units of minimum lithographic feature size F or minimum lithographic dimension F. The minimum lithographic dimension F is defined as the smallest unit of length for which a feature can be defined by a photolithographic process of exposing a photoresist resist layer on the wafer through a mask, developing the resist, removing either the developed or undeveloped portions of the resist, and then etching the areas of the wafer that are uncovered.
A manufacturer selects a minimum feature size as a "ground rule" for each generation of ICs to be produced. The ground rule is determined in consideration of the many elements of the photolithographic process: mask fabrication, illumination sources, optical elements between the illumination source and the wafer, and the properties of the photoresist, as well as the precision of the most critical etch step to be performed. Determination of the ground rule must also necessarily take into account the reliability of the photolithographic process to define features over the desired extent of the wafer, and to operate without error over the desired maintenance cycle of the process equipment. After the ground rule has been selected for a particular generation of ICs, no feature can be defined by the photolithographic process any smaller than that ground rule. As used herein throughout, the terms "minimum feature size F" and "minimum lithographic dimension F" refer to a selected ground rule as described herein.
A DRAM cell structure that is reduced in size in relation to minimum lithographic dimensions is particularly advantageous because it provides a greater increase in the scale of integration than a mere reduction in the ground rule. In addition, even when no reduction is made in the minimum lithographic dimension F for a particular generation of ICs, a substantial reduction in the area occupied by the DRAM cell, in terms of minimum lithographic dimensions (F.sup.2), could provide the increased scale of integration needed to keep pace with Moore's Law.
Some existing deep trench DRAM cell designs, such as those described in U.S. Pat. Nos. 5,264,716 and 5,360,758, incorporate a polysilicon filled deep trench as a storage capacitor which is conductively connected by a deep trench outdiffusion known as a buried strap to the drain of an insulated gate field effect transistor (IGFET) located within a shallow well just below the surface of a monocrystalline silicon substrate. In such structures, the edge of the outdiffusion from the buried strap lies very close (usually less than the minimum lithographic dimension F) to the channel region of the IGFET). In addition, because of the way the buried strap is formed by outdiffusion of dopant ions from inside the deep trench, the outdiffused doping profile extends a direct path from the trench to the channel region. The proximity of the strap and the trench to the channel region of the IGFET tends to decrease the threshold voltage V.sub.T of the n-type IGFET of such memory cells. To restore the threshold voltage Vt to the desired level, the shallow well in which the IGFET is located is implanted with ions to high dopant concentrations. However, the high well dopant concentration greatly increases the junction leakage, subthreshold voltage swing and the substrate sensitivity of the IGFET.
The article by T. Ozaki et al. entitled "0.228 um.sup.2 Trench Cell Technologies with Bottle-Shaped Capacitor for 1 Gbit DRAMs," IEDM Digest of Technical Papers, 1995, pp. 661-664 ("the Ozaki et al. Article") describes a proposed DRAM cell design which has dimensions of 6 F.sup.2. That proposed cell design is similar to the deep trench DRAM cell designs described above in that the conductive path from the deep trench storage capacitor through the transfer device to the bitline contact is essentially a straight line, except that the design described in the Ozaki et al. Article requires a surface strap rather than a buried strap.
In order to achieve the small cell size, the design described in the Ozaki et al. Article requires the edge of the deep trench storage capacitor to be placed very close to the gate conductor which controls the transfer device of the cell. Consequently, errors which occur in the positioning of masks which define the deep trench and the gate conductor (even those which are within overlay tolerances) can substantially decrease the channel width and/or prevent the surface strap between the deep trench and the channel from forming. Consequently, existing process tolerances place great obstacles to the implementation of the design described in the Ozaki et al. Article. In addition, the high probability of such channel shortening errors requires high well dopant concentrations to overcome the expected short channel effects which, as described above, leads to undesirable device degradation. As the integration density increases, a new structure is needed by which the strap and trench regions of the memory cell are further removed from the channel region of the IGFET. In that way, dopant concentrations in the IGFET can be reduced, thereby reducing the junction capacitance and improving device characteristics.
Commonly assigned U.S. Patent Application Serial No. filed Jan. 15, 1998 (Attorney Docket No. FI9-97-226), entitled "Transistor Having Substantially Isolated Body and Method of Making the Same" describes a field effect transistor (FET) structure which is formed in a mesa region of semiconductor material on the sidewall of a shallow trench isolation (STI) region. The mesa region is substantially electrically isolated from the semiconductor substrate. This patent application is hereby incorporated herein by reference.
Commonly-assigned U.S. Patent Application Serial No. filed Jan. 15, 1998 (Attorney Docket No. FI9-97-270) entitled "Semiconductor Integrated Circuits" describes a self-linking active semiconductor device structure which is formed in a substantially continuous mesa region. A FET such as the device described in the above incorporated patent application (Attorney Docket No. FI9-97-226) can be fabricated in the mesa region as the active semiconductor device, for example. This patent application is hereby incorporated herein by reference.
Accordingly, it is an object of the invention to provide a cell structure for a DRAM which occupies reduced area of the wafer surface in terms of minimum lithographic dimensions.
Another object of the invention is to provide an ultra compact DRAM array structure.
Still another object of the invention is to provide a method of fabricating a DRAM cell and related support devices by a single unified process.
Another object of the invention is to provide a structure for a DRAM memory cell in which the separation is proportionately increased between the strap and the channel region of the access transistor.
Another object of the invention is to provide a cell structure for a DRAM by which dopant concentrations within the IGFET device can be reduced in relation to the case where the strap is very close to the channel.
Another object of the invention is to provide a cell structure for a DRAM which has reduced junction capacitance.